For the first time, Samsung researchers will join IBM scientists in the Semiconductor Research Alliance at the Albany Nanotech Complex, Albany, N.Y., where researchers will investigate new materials and transistor structures, as well as innovative interconnect and packaging solutions for next-generation technology nodes. The research developments from this joint activity are planned to enable the delivery of industry leading silicon solutions that are optimized for performance, power consumption and size.
"We are pleased to have our top-level scientists involved with the cutting-edge research that's taking place at the Albany Nanotech Center," said ES Jung, senior vice president of technology development, System LSI Division, Samsung Electronics. "This should further enhance our joint efforts to continue technology leadership well into the future."
New process technology developed by the companies is planned to extend leadership in mobile computing as well as other high performance applications. For consumers, a new generation of devices -- smarter, connected and more mobile -- will require essential semiconductor breakthroughs to keep pace with technology trends (i.e. the mobile web, cloud computing,) and users' loftier expectations around performance and reliability.
"Collaborative innovation will be critical if the semiconductor industry is to continue driving new forms of consumer electronics and new methods of computing," said Michael Cadigan, general manager, IBM Microelectronics. "That's why we're excited to have Samsung scientists working with us at the most fundamental stages of the R&D process."
The agreement also renews IBM and Samsung's joint process development agreement (JDA) to multiple nodes starting at 20nm. IBM and Samsung plan to develop advanced technologies for foundry customers, enabling high-performance, energy-efficient chips at 20nm and beyond. To further enhance the JDA, Samsung's Semiconductor R&D center will also participate in development contribution.
Solutions for CMOS technology at 20-nanometers and beyond will be presented at the Common Platform Technology forum on January 18, 2011 at Santa Clara Convention center.