Samsung, In Collaborat​ion with Physical IP and Design Enablement Partners, Confirms 20nm Design Infrastruc​ture with Test Chip Tape-out
Samsung, In Collaborat​ion with Physical IP and Design Enablement Partners, Confirms 20nm Design Infrastruc​ture with Test Chip Tape-out
  • Korea IT Times
  • 승인 2011.07.13 17:01
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Samsung Electronics Co., Ltd., a global leader in advanced semiconductor solutions, today announced that its foundry business, Samsung Foundry, successfully taped-out a test chip based on its 20nm process with High-k Metal Gate* (HKMG) technology. Together with key ecosystem partners, Samsung Foundry is taking innovative steps to validate a robust design infrastructure for its latest manufacturing technology node. Samsung Foundry's 20nm early access process design kit (PDK) is currently available to those customers who are in the initial stages of designing their next-generation products.  
                                                            
"With more functionality converged into a single device, semiconductor SoC design companies need advanced foundry services that provide comprehensive design enablement portfolios along with proven manufacturing technologies," stated Dr. Kyu-Myung Choi, vice president of System LSI infrastructure design center, Device Solutions, Samsung Electronics. "This is a significant milestone with regards to the design ecosystem that needs to be developed in parallel with the manufacturing process. The design methodology, tools and IPs used on this 20nm test chip bring together the most advanced technology from our design infrastructure partners together with Samsung process and design technology to solve critical design challenges so our customers can deliver their latest chips to market quickly and efficiently."
 
At the 20nm process, an entirely new design infrastructure approach is needed to address impediments in developing and manufacturing next-generation, energy-efficient SoCs. Many new 20nm design kits, router and other design enablement features were used in this first test chip to support novel process innovations such as new device structures, local interconnects, and advanced routing rules.  Due to the investment that Samsung is making into the entire ecosystem at 20nm process, customers will have broad access to all aspects of the design infrastructure.  
 
When developing this first 20nm test chip, Samsung, and its ecosystem partners - ARM, Cadence and Synopsys - implemented a broad suite of design collaterals.  ARM physical IP and processor IP were used to build a prototype SoC test chip. Samsung utilized both the Cadence unified digital design flow and the Synopsys GalaxyTM Implementation Platform to implement different components of the test chip in order to validate Samsung's design methodology for both Cadence and Synopsys design flows.
 
Leveraging the unique IP integration capabilities from ARM, Samsung was able to use ARM physical and processor IP to validate the design readiness of their most advanced node.   ARM provided a full implementation of the test chip, which contained an ARM CortexTM-M0 processor, ARM Artisan prototype libraries (both 12-track high performance and 9-track high density versions), custom memories, GPIO, and test structures.  This comprehensive implementation provided a solid proof point of the silicon characteristics attainable Samsung's advanced 20nm process.
 
Samsung deployed the unified digital flow -- RTL to GDSII -- from Cadence Design Systems. The flow addresses the requirements of advanced 20-nanometer design, such as IP integration and validation, and complex new design rules. Samsung used the Cadence Encounter Digital Implementation System, RTL Compiler, Incisive Enterprise Simulator, QRC Extraction, Encounter Timing System, Encounter Power System, Encounter Test and Physical Verification System. The Cadence NanoRoute Router was also used for 20-nanometer advanced digital routing.
 
Samsung also deployed Synopsys GalaxyTM Implementation Platform, including the Design Compiler synthesis, IC Compiler place-and-route, In-Design physical verification with IC Validator, StarRCTMextraction and PrimeTime signoff tools. Key 20-nm design enablement innovations developed as part of the collaboration with Synopsys include modeling of new device structures, In-Design physical verification technology and coding of advanced routing and design rule checking (DRC).
 


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