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Last September, Samsung made a breakthrough in the 40 nanometer design rule. This September, Samsung will again introduce the world's most smallest memory chip. It is already known that Samsung Electronics is highly competitive in memory chips and semiconductors. They did it again, and this time brought a 30nm memory chip into reality. A senior official of Samsung Electronics announced Wednesday: "We are close to completing the development of 30-nanometer memory chips for the first time in history."
The 30-nanometer technology is roughly one four thousandth the thickness of a human hair. A 30-nanometer technology based 64 gigabit memory chip can hold up to 32,000 pages. According to Hwang's Law, flash chips double in density every year. Hwang's Law was practicable since 1999 because of Samsung and Hwang's efforts. Samsung overcame all the technical difficulties to upgrade memory chip technology.
The industry has seen densities of flash memory improving from 256 megabits in 1999 to 32 gigabits last year. Most of this flash memory was used for portable gadgets like cell phones or digital cameras.
Samsung's major technology for 30 nanometer memory is not charge trap flash (CTF), which the outfit deployed in 2006 for the 40-nanometer design rule. "The CTF technology was scalable to 20 nanometer products back then," Hwang continued. "We employed a solution smoothing out from traditional techniques other than CTF to complete the 30 nanometer design rule although we also try to reach the 30 nanometer milestone with CTF at the same time," the executive said. The introduction of the 30 nanometer memory chip is good news for the falling prices of memory chips and Samsung's semiconductor business. It is expected to be the new cash cow for Samsung.