“Demand for higher and more efficient bandwidth utilization is driving the development of smarter networks based on OTN Switching. However, shortfalls in traditional ASIC and ASSP solutions threaten to stifle innovation,” explained Gilles Garcia, director of Wired Communications at Xilinx, Inc. “With our expanded range of OTN Switching-optimized SmartCORE IP, Xilinx is making the investment needed to enable smarter P-OTS based networks, and thereby enabling customers to develop highly differentiated, compact, low power and All Programmable-based solutions, without compromising on performance or features.”
The new OTN SmartCORE IP blocks are optimized for 7 series devices and include a group of comprehensive and environmentally agnostic APIs – available to abstract all common and complex functions to aid seamless integration into customer software:
● 100G 1 Stage Multiplexer/Demultiplexer SmartCORE IP– Ultra-compact traffic aggregator, supporting any combination of up to 80 channels of ODUj traffic muxed into or demuxed from a high order ODU4.
● OIF compliant 100G SAR SmartCORE IP– 80 channel segmentation and reassembly core which packetizes ODUjs into packet flows. This enables ODU traffic to be switched through a packet switch fabric, facilitating Packet Optical Transport systems.
● 100G ODUMon SmartCORE IP – A bi-directional IP block used to perform overhead insertion and extraction on up to 80 ODUj channels. Used in conjunction with the Xilinx 128ch OTN Overhead Processor, it enables PM Monitoring, TCM Monitoring and/or TCM Termination and Generation with consequent action insertion for up to 6 levels of TCM on each of the ODUj channels.
