TEXAS, US - At Mobile World Congress, Texas Instruments (TI) released the 0.3” HD Tilt & Roll Pixel (TRP) DLP® Pico™ chipset, its smallest, most power-efficient micro-mirror array, which can generate high-definition (HD) displays from compact electronics, including tablets, smartphones, accessories, wearable displays, augmented reality displays, interactive surface computing, digital signage and control panels.
Based on proven DLP Cinema® technology, this new DLP Pico chipset delivers bright, vivid HD image quality. Developers, system integrators, retailers and media interested in meeting TI experts at Mobile World Congress may request a meeting by contacting dlpmwc@list.ti.com.
The new 0.3” HD TRP chipset leverages TI’s proprietary TRP DLP architecture and adaptive IntelliBrightTM suite of algorithms to deliver higher brightness and lower power consumption than previous DLP Pico chipset architectures. Additionally, the chipset’s fast switching speeds of up to thousands of times per second enables the smallest true-color RGB engines with 120-Hz video performance.
To accelerate end-product development, TI maintains the most extensive pico ecosystem in the industry and is actively working with leading developers and manufacturers to bring products to market in 2014 that incorporate the0.3” HD TRP chipset. For more details, please contact a member of DLP’s ecosystem of leading optical engine manufacturers, including Asia Optical, Sekonix, Shenzhen Anhua Optoelectronics Technology Co. LTD, UneedElectro Inc. and Young Optics.
“TI has been a strong and innovative supplier to us,” said Edward Tang, CEO of Avegant. “We are already utilizing the innovative 0.3” HD TRP chipset in our virtual retinal display product, the Avegant Glyph, to beam images directly onto the human eye. We selected this chipset based on its HD image quality, flexibility and power savings.”
“This HD chipset represents a major milestone for DLP; we are achieving two times the number of pixels in a 0.3-inch MEMS device with 30 percent greater optical efficiency and up to 50 percent power savings on a frame-by-frame basis than our previous architectures,” said Frank Moizio, business unit manager of DLP Pico. “This allows developers to create a wider variety of applications and products in smaller form factors than ever before.”
To learn more about the DLP Pico 0.3” HD TRP chipset, please visit www.ti.com/trp-home to review a product brief. To learn how to get started using DLP Pico technology, please visit: www.ti.com/get-started .
