OTTAWA, ON - Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that it successfully demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated in a 16nm CMOS FinFET process.
"Sidense's embedded one-time programmable memory macros have been licensed in customers' designs from 0.18-micron down to 28nm and have been proven at the 20nm process node as well," said Wlodek Kurjanowicz, Sidense Founder and CTO. "Our split-channel 1T-OTP macros were designed to be highly scalable with shrinking process nodes. It is gratifying to see our theories proven in new transistor architectures such as FinFET."
The 3D 16nm FinFET architecture provides higher performance, lower dynamic power and smaller transistor geometries than standard transistors at 20nm, the latter benefit allowing designers to put more functions on a silicon chip. More importantly FinFETs eliminate short-channel effects and the subsequent high leakage currents that limit device scalability of traditional planar transistors. These attributes make devices designed with FinFETs very attractive for market segments that require high performance and minimum power dissipation, such as mobile computing, communications and high-end processor nodes on IoT networks.
Preliminary test results at 16nm confirm correct bit-cell operation with a programming voltage comparable to Sidense 1T-OTP at 28nm with 10X lower leakage current. Programmed bit-cell characteristics are as good as or better than those for 20nm and 28nm bit cells with very large margins between programmed and un-programmed cells and with excellent post-bake bit-cell stability.
"With its enhanced speed performance and reduced power dissipation, TSMC's 16nm technology is an excellent choice for mobile device chip designs," said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. "NVM is now, and will continue to be, a key component in mobile devices, and it is encouraging to see good initial test results on Sidense OTP devices at this process node."
