[Cambridge, UK] Today, Agile Analog, the customizable analog IP company, announced the launch of the first complete analog IP subsystem for RISC-V applications at the RISC-V Summit Europe in Barcelona (5-9 June). This significant milestone showcases the initial subsystem, which includes all the necessary analog IP components for a typical battery-powered IoT system. The subsystem consists of a power management unit (PMU), a sleep management unit (SMU), and data converters. By offering a unique, process-agnostic, customizable, and digitally wrapped analog IP subsystem, Agile Analog aims to address the challenges faced by System on Chip (SoC) designers and provide a comprehensive solution when combined with a RISC-V core.
Director of Product Marketing at Agile Analog, Chris Morrison, explained the significance of this development: "The RISC-V architecture has enabled a surge of new SoC product developments, leading to an increasing demand for accessible and configurable IP solutions. One of the major hurdles faced by digital chip designers is integrating analog circuitry to support their SoC designs."
Morrison emphasized the benefits of Agile Analog's RISC-V analog IP subsystem, stating, "Our RISC-V analog IP subsystem allows users to access the appropriate analog IP for a specific process and foundry, seamlessly integrating it with digital IP from a digital IP provider in the RISC-V space. This simplifies chip design and accelerates the time to market for new RISC-V IoT applications. Like all Agile Analog IP, this subsystem is customizable to meet the precise feature requirements of each application."
For years, traditional analog IP has presented a significant bottleneck, with limited options available to chip designers. The integration of multiple analog IP blocks from various vendors has been a challenging task. Designing and verifying the mixed-signal boundary between analog and digital components has been particularly daunting, known for its time-consuming nature and the need for specialist knowledge and tools. However, Agile Analog's unique technology and digitally wrapped approach offer a solution to these integration and verification challenges, allowing Agile Analog to address and resolve them promptly on behalf of the customer.
The newly introduced analog IP subsystem has been verified in both analog and digital environments, and it directly connects to the MCU's peripheral bus. Additionally, Agile Analog provides a SystemVerilog model for easy integration into an existing SoC's digital verification environment.
Calista Redmond, CEO of RISC-V International, commended the innovative solution, saying, "RISC-V has already made its mark with over 10 billion cores globally, and the RISC-V ecosystem is flourishing. It is crucial to have innovative solutions like Agile Analog's to assist chip designers within our community in fast-tracking the delivery of exciting new RISC-V IoT applications."
Agile Analog will showcase its products and deliver presentations at the RISC-V Summit Europe 2023.
The initial RISC-V subsystem macro for IoT applications by Agile Analog is now available. It consists of the following sub-blocks:
agilePMU:
The agilePMU Subsystem is a highly integrated and efficient power management unit designed for SoCs/ASICs. It features a power-on-reset, multiple low drop-out regulators, and an associated reference generator to ensure low power consumption while delivering optimal power management capabilities. With an integrated digital controller, this subsystem allows precise control over start-up and shutdown processes, supports supply sequencing, and enables individual programmable output voltage for each LDO. Real-time status monitors provide feedback on the current state of the subsystem, ensuring optimal system performance.
agileSMU
The agileSMU Subsystem is a low power integrated macro consisting of the essential IP blocks required to securely manage waking up a SoC from sleep mode. Typically containing a programmable oscillator for low frequency SoC operation and RTC, a number of low power comparators which can be used to initiate the wake-up sequence, and a power-on-reset which provides a robust, start-up reset to the SoC. Equipped with an integrated digital controller, this subsystem offers precise control over wake-up commands and sequencing. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.
agileSensorIF
The agileSensorIF Subsystem is a low power integrated macro providing all the analog required to interface with external sensors. Featuring two up-to 12-bit and 64 MSPS SAR ADCs, a 12-bit DAC and multiple programmable comparators, this sensor interface provides all the connections needed to interface with the outside world. Integrated programmable gain amplifiers and buffers support a wide range of external sensors and systems. It is equipped with an integrated digital controller and status monitors to provide real-time feedback on the current state of the subsystem, ensuring optimal system performance over the full product lifecycle.
